Removal of trilayer resist without damage to underlying structure

ABSTRACT

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region. The middle layer is disposed between the top layer and a bottom layer of the trilayer photoresist structure. The middle layer and the bottom layer in the first region are removed to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region. The first region is filled to protect the at least one first structure. The middle layer in the second region is removed while the at least one first structure remains protected.

BACKGROUND Technical Field

The present invention generally relates to semiconductor processing, andmore particularly to methods and devices that can remove a middle layerin a trilayer photoresist without damage to exposed device structures.

Description of the Related Art

Semiconductor patterning often employs photoresists for creatingdetailed masks for processing semiconductor structures. In someinstances, multiple photoresist layers are employed to process differentareas of a chip or wafer using different portions of the multilayeredstructure. In one example, patterning schemes with photoresists can beemployed to form critical dimension (CD) features, e.g., sources/drains,fins, gates, contacts, back end of the line (BEOL) metal layers, etc.

SUMMARY

In accordance with an embodiment of the present invention, a method forsemiconductor processing includes forming a trilayer resist structurehaving a middle layer disposed between a top layer and a bottom layer.The top layer is removed from a first region to expose the middle layerin the first region, and the middle layer and the bottom layer areremoved in the first region to expose a structure to be processed. Thetop layer in a second region is also removed with the bottom layer inthe first region. The first region is filled to protect the structure inthe first region. The middle layer is removed in the second region whilethe first region remains protected. The structures in the first regionand structures in the second region are exposed.

Another method for semiconductor processing includes forming a trilayerresist structure having a middle layer disposed between a top layer anda bottom layer; removing the top layer from a first region to expose themiddle layer in the first region; removing the middle layer and thebottom layer in the first region, to expose a structure to be protected,the top layer in a second region also being removed with the bottomlayer in the first region; processing the structure to be protected inthe first region; forming a planarization layer over the middle layer inthe second region and the structure to be protected in the first region;removing the planarization layer down to the middle layer in the secondregion and to a position over the structure to be protected in the firstregion; removing the middle layer in the second region while the firstregion remains protected by the planarization layer; and stripping theplanarization layer in the first region and the bottom layer in thesecond region to expose the structure to be protected in the first andsecond regions.

Yet another method for semiconductor processing includes forming atrilayer resist structure having a middle layer disposed between a toplayer and a bottom layer; removing the top layer from a first region toexpose the middle layer in the first region; removing the middle layerand the bottom layer in the first region, to expose a structure to beprotected, the top layer in a second region also being removed with thebottom layer in the first region; processing the structure to beprotected in the first region; forming a planarization layer over themiddle layer in the second region and the structure to be protected inthe first region such that the first region remains protected by theplanarization layer; polishing to remove the middle layer in the secondregion wherein the planarization layer in the first region and thebottom layer in the second region are planarized; and stripping theplanarization layer in the first region and the bottom layer in thesecond region to expose the structure to be protected in the first andsecond regions.

Yet another method for semiconductor processing includes removing, froma first region of a semiconductor device, a top layer of a trilayerphotoresist structure formed in the first region and a second region ofthe semiconductor device to expose a middle layer of the trilayerphotoresist structure in the first region, the middle layer beingdisposed between the top layer and a bottom layer of the trilayerphotoresist structure; removing the middle layer and the bottom layer inthe first region to expose at least one first structure, the top layerin the second region being removed during the removal of the bottomlayer in the first region; filling the first region to protect the atleast one first structure; and removing the middle layer in the secondregion while the at least one first structure remains protected.

Yet another method for semiconductor processing includes removing, froma first region of a semiconductor device, a top layer of a trilayerphotoresist structure formed in the first region and a second region ofthe semiconductor device to expose a middle layer of the trilayerphotoresist structure in the first region, the middle layer beingdisposed between the top layer and a bottom layer of the trilayerphotoresist structure; removing the middle layer and the bottom layer inthe first region to expose at least one first structure, the top layerin the second region being removed during the removal of the bottomlayer in the first region; processing the at least one first structure;forming a planarization layer over the middle layer in the second regionand the at least one first structure; removing the planarization layerin the second region, and removing the planarization layer in the firstregion down to a position located between the middle layer in the secondregion and the at least one first structure; and removing the middlelayer in the second region by performing a selective etch process whilethe at least one first structure remains protected by the planarizationlayer in the first region.

Yet another method for semiconductor processing includes removing, froma first region of a semiconductor device, a top layer of a trilayerphotoresist structure formed in the first region and a second region ofthe semiconductor device to expose a middle layer of the trilayerphotoresist structure in the first region, the middle layer beingdisposed between the top layer and a bottom layer of the trilayerphotoresist structure; removing the middle layer and the bottom layer inthe first region to expose at least one first structure, the top layerin the second region being removed during the removal of the bottomlayer in the first region; processing the at least one first structure;forming a planarization layer over the middle layer in the second regionand the at least one first structure; removing the planarization layerin the second region, and removing the planarization layer in the firstregion down to a position located between the middle layer in the secondregion and the at least one first structure; and removing the middlelayer in the second region by performing a polishing process while theat least one first structure remains protected by the planarizationlayer in the first region.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description will provide details of preferred embodimentswith reference to the following figures wherein:

FIG. 1 is a cross-sectional view illustratively showing an n-type fieldeffect transistor (NFET) region and a p-type field effect transistor(PFET) region on a semiconductor device where the PFET region has a toplayer of a trilayer structure removed in accordance with an embodimentof the present invention;

FIG. 2 is a cross-sectional view of the device of FIG. 1 showing amiddle layer and a bottom layer removed from the PFET region on thesemiconductor device and a top layer in the NFET region removed inaccordance with an embodiment of the present invention;

FIG. 3 is a cross-sectional view of the device of FIG. 2 showingunderlying structures processed (e.g., a spacer etch, etc.) in the PFETregion on the semiconductor device in accordance with an embodiment ofthe present invention;

FIG. 4 is a cross-sectional view of the device of FIG. 3 showing aplanarization layer formed for protection in the PFET region and on themiddle layer in the NFET region in accordance with an embodiment of thepresent invention;

FIG. 5 is a cross-sectional view of the device of FIG. 4 showing theplanarization layer etched to below the middle layer in the NFET regionin accordance with an embodiment of the present invention;

FIG. 6 is a cross-sectional view of the device of FIG. 5 showing themiddle layer in the NFET region removed in accordance with an embodimentof the present invention;

FIG. 7 is a cross-sectional view of the device of FIG. 6 showing theplanarization layer and the bottom layer stripped to expose theunderlying structures in accordance with an embodiment of the presentinvention;

FIG. 8 is a cross-sectional view of the device of FIG. 4 showing theplanarization layer and the bottom layer planarized to remove the middlelayer of the NFET region in accordance with another embodiment of thepresent invention;

FIG. 9 is a cross-sectional view of the device of FIG. 8 showing theplanarization layer and the bottom layer stripped to expose theunderlying structures in accordance with an embodiment of the presentinvention; and

FIG. 10 is a block/flow diagram showing methods for forming asemiconductor device in accordance with embodiments of the presentinvention.

DETAILED DESCRIPTION

In accordance with aspects of the present invention, trilayerphotoresist structures and processing methods are provided forprocessing semiconductor devices. In particularly useful embodiments,the processing methods can be employed in complementary metal oxidesemiconductor (CMOS) device processing, especially where NFET and PFETareas of the device are alternately processed.

In accordance with the present embodiments, a trilayer resist (TLR)patterning scheme is provided to enable formation of device dimensionsincluding critical dimension features. The device dimensions can be forstructures such as, e.g., source and drain regions, fins, gates,contacts, back end of the line (BEOL) metal layers, etc. especially withcritical dimensions (CDs) of less than, e.g., 40 nm and with minimalline edge roughness (LER) and minimal line width roughness (LWR).

In one embodiment, the TLR patterning scheme utilizes anorganic/inorganic/organic multilayer stack instead of just an organiclayer. A top organic layer photoresist material can be of a typesuitable for deep ultraviolet (DUV), extreme UV (EUV), X-ray, or e-beamlithography that can be located atop an antireflective coating (ARC),which is also comprised of an organic material providing high resolutionlithography patterning. A middle inorganic layer of the TLR comprisesany oxide layer such as, for example, a low temperature (e.g., less thanor equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxidederived from TEOS (tetraethylorthosilicate), a silicon oxide, a silaneoxide, or a Si-containing ARC material (SiARC).

The middle inorganic layer includes a patterning hard mask for retainingCD and vertical profile during organic planarization layer (OPL) etching(e.g., by reactive ion etching (RIE)) of a bottom organic layer. Thebottom organic layer of the TLR (e.g., OPL) can include any spin-onorganic layer such as, for example, a Near Frictionless Carbon (NFC), adiamond-like carbon, a thermosetting polyarylene ether, or a polyimide.

The trilayer structure is employed and processed to protect differentstructures during the back and forth of CMOS processing (e.g., betweenalternate NFET and PFET processing in different areas of a chip orwafer).

It is to be understood that aspects of the present invention will bedescribed in terms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps can be varied within the scope of aspects of the presentinvention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements can also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements can be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments can include a design for an integrated circuitchip, which can be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer can transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

It should also be understood that material compounds will be describedin terms of listed elements, e.g., SiGe. These compounds includedifferent proportions of the elements within the compound, e.g., SiGeincludes Si_(x)Ge_(1-x) where x is less than or equal to 1, etc. Inaddition, other elements can be included in the compound and stillfunction in accordance with the present principles. The compounds withadditional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”,as well as other variations thereof, means that a particular feature,structure, characteristic, and so forth described in connection with theembodiment is included in at least one embodiment. Thus, the appearancesof the phrase “in one embodiment” or “in an embodiment”, as well anyother variations, appearing in various places throughout thespecification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This can be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, can be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or features) as illustrated in the FIGS. It will be understood that thespatially relative terms e intended to encompass different orientationsof the device in use or operation in addition to the orientationdepicted in the FIGS. For example, if the device in the FIGS. is turnedover, elements described as “below” “beneath” other elements or featureswould then be oriented “above” the other elements or features. Thus, theterm “below” can encompass both an orientation of above and below. Thedevice can be otherwise oriented (rotated 90 degrees or at otherorientations), and the spatially relative descriptors used herein can beinterpreted accordingly. In addition, it will also be understood thatwhen a layer is referred to as being “between” two layers, it can be theonly layer between the two layers, or one or more intervening layers canalso be present.

It will be understood that, although the terms first, second, etc. canbe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, a first element discussed belowcould be termed a second element without departing from the scope of thepresent concept.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, in accordance with oneembodiment, a semiconductor device 10 is illustratively shown. Device 10can include a CMOS device. The CMOS device 10 includes an NFET region 20and a PFET region 22. The NFET region 20 and PFET region 22 both includegate structures 24 having a protective spacer layer 26 formed thereon.The spacer layer 26 can include a nitride, such as silicon nitride,although other suitable dielectric materials may be employed. The NFETregion 20 and PFET region 22 can have any structures formed therein;however, for illustrative purposes the structures 24 include spacerlayers 26, hard mask or cap layers 30 and shallow trench isolation (STI)regions 28, which are often subjected to damage by conventionalprocessing. It should be understood that other structures and componentscan also be employed instead of or in addition to the illustrativestructures 24 described.

It should also be understood that the STI regions 28 can be formed on asubstrate including one or more layers and materials. In one embodiment,the STI region 28 is formed on a semiconductor substrate, such as, e.g.,Si, SiGe, Ge, III-V materials or any other suitable material(s).

The cap layers 30 may be formed over dummy gates or metal gates 32.Other structures can also be employed. The cap layers 30 can includesilicon nitride, although other suitable materials may be employed.

In accordance with illustrative embodiments, a trilayer (TLR) resiststructure 12 includes a bottom layer 14, a middle layer 16 and a toplayer 18 that are formed across the NFET region 20 and the PFET region22. In one embodiment, the TLR structure 12 utilizes anorganic/inorganic/organic multilayer stack. The bottom layer 14 mayinclude an organic planarization layer (OPL). The bottom layer 14 caninclude a spun-on organic layer such as, for example, a NearFrictionless Carbon (NFC), a diamond-like carbon, a thermosettingpolyarylene ether or polyimide.

The middle inorganic layer 16 can include any oxide layer such as, forexample, a low temperature (e.g., less than or equal to 250° C.)chemical vapor deposited (CVD) oxide, an oxide derived from TEOS(tetraethylorthosilicate), a silicon oxide, a silane oxide, aSi-containing ARC material (SiARC), etc. The middle inorganic layer 16can include a patterning hard mask for retaining CDs and verticalprofiles during the etching or removal of the underlying bottom layer 14(e.g., OPL). In one embodiment, the middle inorganic layer 16 isselectively etchable to one or both of the top layer 18 and bottom layer14.

The top layer resist material 18 can be of a type suitable for deepultraviolet (DUV), extreme UV (EUV), X-ray, or e-beam lithography. Thetop layer 18 can include an organic material. In one embodiment, the toplayer 18 can be formed on an ARC middle layer 16 (e.g., SiARC), or anadditional ARC layer (not shown) (e.g., an organic ARC material) may beformed between the top layer 18 and middle layer 16. The top layer 18can include an organic material that provides for high resolutionlithography patterning.

The trilayer resist (TLR) structure 12 enables the formation of devicedimensions including critical dimension features. The device dimensionscan be for structures such as, e.g., source and drain regions, fins,gates, contacts, back end of the line (BEOL) metal layers, etc.especially with CDs of less than about, e.g., 40 nm and minimal lineedge roughness (LER) and minimal line width roughness (LWR). Thetrilayer structure 12 is employed and processed to protect differentstructures during the back and forth of CMOS processing (e.g., betweenalternate NFET and PFET processing).

After being deposited in both the NFET region 20 and the PFET region 22of CMOS device 10, FIG. 1 depicts the trilayer structure 12 having thetop layer 18 removed from the PFET region 22. This can be achieved by aconventional photolithography process by exposing the resist through aphotomask, developing the resist and removing the light-exposed resistof the PFET region 22 while leaving the resist intact in the NFET region20. This results in the top layer 18 being removed from the PFET region22 to expose the middle layer 16.

Referring to FIG. 2, a reactive ion etch (RIE) is performed to removethe middle layer 16 and the bottom layer 14 from the PFET regions 22.The RIE also removes the top layer 18 from the NFET region 20, whichstops on the middle layer 16. In the illustrative example depicted, thestructures 24 are protected by the spacer layer 26.

Referring to FIG. 3, another RIE process (spacer RIE) is employed toremove the spacer layer 26 from horizontal surfaces. The RIE formssidewalls spacers 34 on the structures 24. The middle layer 16 on theNFET region 20 protects the bottom layer 14 in the NFET region 20. Aportion of the thickness of the middle layer 16 is consumed during thespacer RIE.

To continue processing, the middle layer 16 and/or the bottom layer 14in the NFET region 20 need to be removed. Due to the etch resistantproperties of the middle layer 16 and the depth of the bottom layer 14,etching the middle layer 16 (and/or the bottom layer 14) in the NFETregion 20 directly can cause damage to the cap layers (hard mask) 30,the STI regions 28, spacers 34 and other structures as indicated byregions 35. To prevent damage in regions 35, different methods areemployed in accordance with aspects of the present invention.

Referring to FIG. 4, a planarization layer 36 is formed over the middlelayer 16 in the NFET region 20 and over the exposed structures 24 in thePFET region 22. The planarization layer 36 can include an OPL, e.g., forbottom layer 14, although any suitable dielectric material can beemployed for the planarization layer 36. To achieve a uniform planarityover various pattern densities, chemical-mechanical polish (CMP) can beemployed over the top surface.

Referring to FIG. 5, in one embodiment, the planarization layer 36 isetched, to reduce a height of a surface 38 of the planarization layer 36in the PFET region 22 to below a height of the middle layer 16 in theNFET region 20. The etch can be selective to the planarization layer 36so that the middle layer 16 remains substantially intact. The height ofthe surface 38 of the planarization layer 36 can be anywhere between themiddle layer 16 and the features to be protected (e.g., cap layer orhard mask 30).

In a particularly useful embodiment, the planarization layer 36 issubjected to a RIE to reveal the middle layer 16 in the NFET region 20.Then, another etch (e.g., RIE or wet etch) is performed to selectivelyetch the planarization layer 36 to achieve the height on surface 38.

Referring to FIG. 6, the middle layer 16 is removed from the NFET region20 by a selective etch process (e.g., selective to the material of layer36 and/or layer 14). Any suitable etch process may be employed. In oneembodiment, the materials for the bottom layer 14 and the planarizationlayer 36 are the same. In other embodiments, the materials for thebottom layer 14 and the planarization layer 36 are different. In oneparticularly useful embodiment, a height of a surface 40 of the bottomlayer 14 exceeds a height of a surface 42 of the planarization layer 36.In other embodiments, the materials of the bottom layer 14 and theplanarization layer 36 can be selected to provide a desired amount ofprotection to regions 20 and 22. For example, one of the bottom layer 14or the planarization layer 36 may be completely removed before the otherbased upon the materials and heights of the layers 14 and 36.

Referring to FIG. 7, the bottom layer 14 of the NFET region 20 and theplanarization layer 36 in the PFET region 22 are stripped to expose theunderlying structures 24. The underlying structures (e.g., structures24, STI region 28, etc.) remain intact and virtually undamaged as aresult of the use of the planarization layer 36 and processing sequence.Processing can continue with blocking the PFET region 22 and performinga spacer etch in the NFET region 20.

It should be understood that the NFET and the PFET regions described maybe reversed and processed in a similar manner. In other embodiments, thealternatively processed regions may include regions other than NFET andPFET regions.

In another method, processing begins with the structure of FIG. 5.

Referring to FIG. 8, a planarization process on the structure of FIG. 5,such as chemical mechanical polishing (CMP) is performed to remove aportion of the planarization layer 36 and the middle layer 16 in theNFET region 20. A surface 48 extends across the NFET region 20 on bottomlayer 14 and across the PFET region 22 on planarization layer 36.

In one embodiment, the materials for the bottom layer 14 and theplanarization layer 36 are the same. In other embodiments, the materialsfor the bottom layer 14 and the planarization layer 36 are different. Inone embodiment, the materials of the bottom layer 14 and theplanarization layer 36 can be selected to provide a desired amount ofprotection to regions 20 and 22. For example, one of the bottom layer 14or the planarization layer 36 may be completely removed before the otherbased upon the materials of the layers 14 and 36.

Referring to FIG. 9, the bottom layer 14 of the NFET region 20 and theplanarization layer 36 in the PFET region 22 are stripped to expose theunderlying structures 24. The underlying structures (e.g. structures 24,STI region 28, etc.) remain intact and virtually undamaged as a resultof the use of the planarization layer 36 and processing sequence.Processing can continue with PFET source/drain epitaxial growth,deposition of a cap layer and then continue with patterning for blockingthe PFET region 22 and performing a spacer etch in the NFET region 20 togrow an NFET source/drain epitaxy layer.

It should be understood that the NFET and the PFET regions described maybe reversed and processed in a similar manner. In other embodiments, thealternatively processed regions may include regions other than NFET andPFET regions.

Aspects or the present invention address middle inorganic layer removalprocesses that can damage underlying structures. The examples describedin a trilayer patterning example for dual source drain spacer formationfor CMOS devices is non-limiting. The present invention can apply to anypatterning structure which can cause potential damage to underlyingstructures during middle inorganic layer removal processes.

Referring to FIG. 10, methods for semiconductor processing areillustratively shown and described. In some alternative implementations,the functions noted in the blocks may occur out of the order noted inthe figures. For example, two blocks shown in succession may, in fact,be executed substantially concurrently, or the blocks may sometimes beexecuted in the reverse order, depending upon the functionalityinvolved. It will also be noted that each block of the block diagramsand/or flowchart illustration, and combinations of blocks in the blockdiagrams and/or flowchart illustration, can be implemented by specialpurpose hardware-based systems that perform the specified functions oracts or carry out combinations of special purpose hardware and computerinstructions.

In block 102, a trilayer resist structure is formed having a middlelayer disposed between a top layer and a bottom layer. The trilayerresist structure can be formed by spun-on resist materials or depositedmaterials depending on the materials selected. The trilayer resiststructure can include an organic layer, inorganic layer and organiclayer, respectively, for the top layer, the middle layer and the bottomlayer. In one embodiment, the middle layer is resistant to etchantsemployed to etch the top layer and/or the bottom layer. The middle layercan include an anti-reflection coating. The trilayer resist structure isprovided to protect or pattern underlying structures, such as, e.g., asemiconductor substrate or device.

In block 104, the top layer is removed from a first region to expose themiddle layer in the first region. The top layer can be removed byblocking the second region and etching (e.g., selectively) the top layerin the first region. The first region can include any designated regionthat needs protection or different processing, e.g., NFET or PFETregions of a CMOS device.

In block 106, the middle layer and the bottom layer in the first regionare removed to expose a structure to be subsequently processed (e.g.,spacer RIE in one example). The middle layer can be selectively etchedwith respect to the bottom layer, then the bottom layer may be removed.The second region is protected by the middle layer and/or the blockinglayer (during the subsequent processing in the first region). The toplayer in a second region is also removed down to the middle layer withthe removal of the bottom layer in the first region. The first region isopened to permit additional processing in block 107, such as, e.g.,etching of spacers in the first region, e.g., PFET spacer RIE process.

In block 108, the first region is filled to protect the structure thathas been processed, e.g., protect the first region. This can includeforming a planarization layer over the device. In block 110, the middlelayer is removed in the second region while the first region remainsprotected. This can be performed by etching away the middle layerselective to the planarization layer or by polishing (e.g., CMP) untilthe middle layer is removed.

In block 112, the structures protected in the first region and in thesecond region are exposed. This can be performed by a planarizationlayer/bottom layer strip process (e.g., an etch process). The bottomlayer and the planarization layer can include a same material (e.g.,OPL). The protected structures remain intact without undue damage thatcould otherwise result during the removal of the middle layer or otherstructures. In block 114, processing continues with the furtherprocessing or formation of underlying structures, e.g., field effecttransistors, metal lines or structures, etc.

Having described preferred embodiments for removal of trilayer resistwithout damage to underlying structure (which are intended to beillustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

What is claimed is:
 1. A method for semiconductor processing,comprising: removing, from a first region of a semiconductor device, atop layer of a trilayer photoresist structure formed in the first regionand a second region of the semiconductor device to expose a middle layerof the trilayer photoresist structure in the first region, the middlelayer being disposed between the top layer and a bottom layer of thetrilayer photoresist structure; removing the middle layer and the bottomlayer in the first region to expose at least one first structure, thetop layer in the second region being removed during the removal of thebottom layer in the first region; filling the first region to protectthe at least one first structure; and removing the middle layer in thesecond region while the at least one first structure remains protected.2. The method as recited in claim 1, wherein the trilayer photoresiststructure includes an organic layer, inorganic layer and organic layer,respectively, for the top layer, the middle layer and the bottom layer.3. The method as recited in claim 1, wherein the middle layer isresistant to etchants employed to etch the top layer and the bottomlayer;
 4. The method as recited in claim 1, wherein filling the firstregion includes depositing a planarization layer.
 5. The method asrecited in claim 1, wherein the bottom layer and the planarization layerinclude a same material.
 6. The method as recited in claim 1, whereinthe bottom layer and the planarization layer include an organicplanarization layer (OPL).
 7. The method as recited in claim 1, whereinthe middle layer includes an anti-reflection coating.
 8. The method asrecited in claim 1, further comprising exposing the at least one firststructure and at least one second structure in the second region.
 9. Amethod for semiconductor processing, comprising: removing, from a firstregion of a semiconductor device, a top layer of a trilayer photoresiststructure formed in the first region and a second region of thesemiconductor device to expose a middle layer of the trilayerphotoresist structure in the first region, the middle layer beingdisposed between the top layer and a bottom layer of the trilayerphotoresist structure; removing the middle layer and the bottom layer inthe first region to expose at least one first structure, the top layerin the second region being removed during the removal of the bottomlayer in the first region; processing the at least one first structure;forming a planarization layer over the middle layer in the second regionand the at least one first structure; removing the planarization layerin the second region, and removing the planarization layer in the firstregion down to a position located between the middle layer in the secondregion and the at least one first structure; and removing the middlelayer in the second region by performing a selective etch process whilethe at least one first structure remains protected by the planarizationlayer in the first region.
 10. The method as recited in claim 9, whereinthe trilayer photoresist structure includes an organic layer, inorganiclayer and organic layer, respectively, for the top layer, the middlelayer and the bottom layer.
 11. The method as recited in claim 9,wherein the middle layer is resistant to etchants employed to etch thetop layer and the bottom layer;
 12. The method as recited in claim 9,wherein processing the at least one first structure includes performinga spacer etch.
 13. The method as recited in claim 9, wherein the bottomlayer and the planarization layer include a same material.
 14. Themethod as recited in claim 9, wherein the bottom layer and theplanarization layer include an organic planarization layer (OPL), andthe middle layer includes an anti-reflection coating.
 15. The method asrecited in claim 9, further comprising exposing the at least one firststructure and at least one second structure in the second region,including removing the planarization layer in the first region and thebottom layer in the second region.
 16. A method for semiconductorprocessing, comprising: removing, from a first region of a semiconductordevice, a top layer of a trilayer photoresist structure formed in thefirst region and a second region of the semiconductor device to expose amiddle layer of the trilayer photoresist structure in the first region,the middle layer being disposed between the top layer and a bottom layerof the trilayer photoresist structure; removing the middle layer and thebottom layer in the first region to expose at least one first structure,the top layer in the second region being removed during the removal ofthe bottom layer in the first region; processing the at least one firststructure; forming a planarization layer over the middle layer in thesecond region and the at least one first structure; removing theplanarization layer in the second region, and removing the planarizationlayer in the first region down to a position located between the middlelayer in the second region and the at least one first structure; andremoving the middle layer in the second region by performing a polishingprocess while the at least one first structure remains protected by theplanarization layer in the first region.
 17. The method as recited inclaim 17, wherein the trilayer photoresist structure includes an organiclayer, inorganic layer and organic layer, respectively, for the toplayer, the middle layer and the bottom layer.
 18. The method as recitedin claim 17, wherein the middle layer is resistant to etchants employedto etch the top layer and the bottom layer.
 19. The method as recited inclaim 17, wherein the bottom layer and the planarization layer includean organic planarization layer (OPL), and wherein the middle layerincludes an anti-reflection coating.
 20. The method as recited in claim17, further comprising exposing the at least one first structure and atleast one second structure in the second region, including removing theplanarization layer in the first region and the bottom layer in thesecond region.